1. Field of Invention
This invention pertains generally to semiconductor devices and, more particularly, to a flash memory cell with a contactless bit line.
2. Related Art
Electrically programmable read only memory (EPROM) has been widely used as nonvolatile memory which can keep data unchanged even though the power is turned off. However, EPROM devices have a major disadvantage in that they have to be exposed to Ultra-Violet (UV) light for about 20 minutes for data erasure. This is very inconvenient because an EPROM device has to be unplugged from its socket and moved to the UV light source when the data needs to be changed.
Electrically erasable programmable read only memory (EEPROM) overcomes this problem and permits data to be erased electrically in a much shorter period of time, typically less than 2 seconds. However, it still has a disadvantage in that the data must be erased on a byte-by-byte basis.
Flash EEPROM is similar to EEPROM in that data is erased electrically and relatively quickly. However, with flash EEPROM, the data is erased in blocks which typically range in size from 128 bytes to 64K bytes per block, rather than on a byte-by-byte basis.
In general, there are two basic types of nonvolatile memory cell structures: stack-gate and split-gate. The stack-gate memory cell usually has a floating gate and a control gate, with the control gate being positioned directly above the floating gate. In a split-gate cell the control gate is still positioned above the floating gate, but it is offset laterally from it. The fabrication process for a stack-gate cell is generally simpler than that for a split-gate cell. However, a stack-gate cell has an over-erase problem which a split-gate cell does not have. This problem is commonly addressed by maintaining the threshold voltage of the cell in a range of about 1.0-2.0 volts after an erase cycle, which adds complexity to the circuit design.
Although a split-gate memory cell has no over erase problem, it generally includes an additional gate known as a select gate. Such cells are typically fabricated in double-poly or triple-poly processes which involve relatively complex processing steps. In addition, split-gate cells are generally larger than stack-gate cells. Nevertheless, because of the relatively simple circuit design which is possible when there is no over-erase problem, split-gate cells are used widely, particularly in embedded nonvolatile memory applications.
Split-gate memory cells are commonly formed by first defining the floating gate pattern using a photolithographic mask and then defining the control gate (or select gate) pattern using another photolithographic mask. See, for example, U.S. Pat. Nos. 4,794,565, 5,029,130, and 5,455,792. This approach, however, has substantial limitations and disadvantages. During the photolithographic step in which the floating gate is defined, the corners of floating gate tend to become rounded. Also, pattern shifting can occur during the photolithographic steps, resulting in misalignment between the floating gate, the active area, and the control (or select) gate. Furthermore, in a typical cell array layout in which two adjacent memory cells share the same drain or source regions, the cumulative misalignment will make one cell worse than the other. In some cases, the effect of the misalignment may be so bad that in some of the memory cells in an array, the floating gate or the select gate may have a very short channel length and/or punchthrough may occur, with the result that the logic state of the memory cell may not be clearly identified. This makes the control of manufacturing process much more difficult and/or can force the cell array layout to be made much larger in order to provide more tolerance for the process variation. In U.S. Pat. No. 5,364,806, for example, the memory cell has two floating gate transistors which are separated by and share the same select gate which crosses over the stacked control gate and floating gate, the select gate channel area, and the bit-line diffusions.
A memory cell is erased by forcing electrons to migrate away from the floating gate so that it becomes charged with positive ions. This is commonly accomplished by Fowler-Nordheim tunneling in which a tunnel oxide having a thickness on the order of 70-120 xc3x85 is formed between the monocrystalline silicon substrate and the floating gate. A relative strong electric field (greater than 10 mV/cm) is then applied to the tunnel oxide, and the electrons tunnel from the floating gate toward the underlying source, drain or channel region. This technique is widely used both in stack-gate cells and in split-gate cells, and is described in greater detail in U.S. Pat. Nos. 5,402,371, 5,284,784, 5,455,792 and 5,364,806.
Another way of forming an erase path is to grow a dielectric film between two polysilicon (poly-Si) layers as a tunneling dielectric. U.S. Pat. No. 5,029,130 discloses the formation of a sharp edge on the floating gate to enhance the local electric field around it, with the erase path being formed between the sharp edge and the control gate. By adding a third polycrystalline silicon layer as an erase layer which crosses over, or overlies, the floating gate and the control gate, an erase path can be formed between the side wall of floating gate and the erase layer. This technique is disclosed in U.S. Pat. Nos. 5,847,996 and 5,643,812.
Fowler-Nordheim tunneling can also be used to program a memory cell by forcing electrons to tunnel into the floating gate so that it becomes charged negatively. U.S. Pat. No. 5,402,371, for example, shows electrons being forced to tunnel into the floating gate from the channel region beneath it. This technique is used widely in stack-gate cells as well as in split-gate cells.
Another way of programming a split-gate memory cell is by the use of channel hot carrier injection. During a program operation, the electrons flowing from the source to the drain are accelerated by a high electric field across the channel region, and some of them become heated near the drain junction. Also, the floating gate voltage is usually high during a program operation because of the coupling voltage that is supplied to it either from the control gate or from the source or drain region that is partially overlapped by the floating gate. Some of the hot electrons can get accelerated by the resulting vertical electric field so that they then exceed the energy barrier of the gate oxide and get injected into the floating gate. Examples of this technique are found in U.S. Pat. Nos. 4,794,565, 5,029,130, 5,455,792 and 5,364,806.
FIG. 1 illustrates a split-gate memory cell having a polysilicon select gate 12 positioned to one side of a floating gate 13 and a control gate 14. In the program mode, the control gate is biased at a high voltage (about 18 volts), and source 16, drain 17 and select gate 12 are biased at 0 volts. A strong electric field is thus established across gate oxide 18, where Fowler-Nordheim tunneling takes place, causing electrons to tunnel from the channel region into the floating gate.
In the erase mode, a positive voltage of about 9 volts is applied to the P-well 19, a negative voltage of about xe2x88x929 volts is applied to the control gate, and the source, drain and select gate are kept open. In this mode, the high electric field across gate oxide 18 will initiate Fowler-Nordheim tunneling, and electrons will tunnel from the floating gate to the channel region beneath it.
FIG. 2 illustrates a split-gate memory cell having a floating gate 21, a control gate 22 and a select gate 23, with a portion of the select gate crossing over the control gate. In the program mode, the control gate is biased at a high voltage of about 12 volts, the select gate and the drain node 24 are biased at about 3 volts, and the source node 26 is grounded. With these bias voltages, most of the drain-to-source voltage falls in the mid-channel region 27, where a strong electric field is established. Being coupled to the control gate, the floating gate is at a voltage which is higher than the voltage in the mid-channel region, forming a vertical electric field. Electrons flowing from the source to the drain are accelerated by the high electric field in the mid-channel region and become heated, and some of them are injected into the floating gate due to acceleration by the vertical electric field.
In the erase mode, the control gate is biased at a negative voltage of about xe2x88x9212 volts, the drain node is biased at about 3 volts, and the select gate and the source node are grounded. A high voltage is now established across the tunnel oxide 28 between the floating gate and the drain region beneath the floating gate. This causes electrons to tunnel from the floating gate into the portion of the drain region beneath it.
It is in general an object of the invention to provide a new and improved memory cell array and process of fabrication.
Another object of the invention is to provide a memory cell array and process of the above character which overcome the limitations and disadvantages of the prior art.
These and other objects are achieved in accordance with the invention by providing a memory cell array and process of fabrication in which a floating gate is formed on a substrate for each of a plurality of memory cells, a control gate is formed above and in vertical alignment with each of the floating gates, source regions are formed in the substrate between and partially overlapped by first edge portions of the floating gates in adjacent ones of the cells, bit lines are formed in the substrate midway between second edge portions of the floating gates in adjacent ones of the cells, and a select gate is formed across the control gates, the floating gates, the bit lines and the source regions.